Efficient Place and Route for Pipeline Reconfigurable Architectures
نویسندگان
چکیده
In this paper, we present a fast and eficient compilation methodology for pipeline reconfigurable architectures. Our compiler back-end is much faster than conventional CAD tools, and fairly eficient. W e represent pipeline reconfigurable architectures by a generalized VLI W-like model. The complex architectural constraints are effectively expressed in terms of a single graph parameter: the routing path length (RPL) . Compiling to our model using R P L , we demonstrate fast compilation times and show speedups of between lox and 200x on a pipeline reconfigurable architecture when compared to an UltraSparc-II.
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